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| EL1056AC EL1056C EL1056AC EL1056C Monolithic High-Speed Pin Driver Features Wide g12V output levels 250 ps dispersion 3 ns delay times 1V ns slew rate adjustable Low overshoot and aberrations in 50X systems 3-state output Power-down mode reduces output leakage to nanoamperes Overcurrent sense flag available to protect internal output devices Buffered analog inputs Differential logic inputs are compatible with ECL TTL and CMOS General Description The EL1056 is designed to drive high-quality test signals into close or terminated loads It has a dispersion of 250 ps or less whether due to signal size or direction of edge It can output a very wide 24V output span encompassing all logic families as well as analog levels The EL1056 is fabricated in Elantec's oxide isolated process which eliminates the possibility of latch-up and provides a very durable circuit The output can be turned off in two ways the OE pins allow the output to be put in a high-impedance state which makes the output look like a large resistance in parallel with 3 pF even for back-driven signals with as much as 2 5V ms slew rate The E pins put the output in an even higher impedance state guaranteed to 150 nA leakage in the EL1056A This allows accurate measurements on the bus without disconnecting the EL1056 with a relay The EL1056 incorporates an output current sense which can warn the system controller that excessive output current is flowing The trip point is set by two external resistors Applications Memory testers ASIC testers Functional board testers Analog digital incoming component verifiers Logic emulators Connection Diagram 24-Lead Thermal SOL Package Ordering Information Part No EL1056CM Temp Range 0 C to a 75 C Package Outline 24-Lead MDP0027 Thermal SOL 24-Lead MDP0027 Thermal SOL EL1056ACM 0 C to a 75 C March 1993 Rev A and Heat-spreader 1056 - 1 Top View Note All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ``controlled document'' Current revisions if any to these specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation 1993 Elantec Inc EL1056AC EL1056C Monolithic High-Speed Pin Driver Absolute Maximum Ratings (TA e 25 C) Voltage between V a and Vb Supply Voltage Supply Voltage Supply Voltage Input Current Input Voltage Power-Down Mode Input Voltage Shunt a Shuntb Input Voltage Data Data Input Voltages OE OE Input Voltages VS Vb Ba Bb ISR VSR a 33V b 18V VINH to V a Vb to VINL EE Sense VINH VINL IOUT TJ TA TST PD Input Voltages Output Voltage Input Voltage Input Voltage Output Current Junction Temperature Operating Ambient Temperature Range Storage Temperature Power Dissipation (TA e 25 C) (See Curves) Vb to V a or g6V Differential 0 mA to 3 mA b 0 3V to a 6V (B a ) b5V to B a Bb to (Bb) a 5V Vb to V a or g6V Differential Vb to V a or g6V Differential Vb to V a VINL b0 3V to B a Bb to VINH a 0 3V b 60 mA to a 60 mA 150 C b 0 C to a 75 C b 65 C to a 150 C 3 1W Important Note All parameters having Min Max specifications are guaranteed The Test Level column indicates the specific device testing actually performed during production and Quality inspection Elantec performs most electrical tests using modern high-speed automatic test equipment specifically the LTX77 Series system Unless otherwise noted all tests are pulsed tests therefore TJ e TC e TA Test Level I II III IV V Test Procedure 100% production tested and QA sample tested per QA test plan QCX0002 100% production tested at TA e 25 C and QA sample tested at TA e 25 C TMAX and TMIN per QA test plan QCX0002 QA sample tested per QA test plan QCX0002 Parameter is guaranteed (but not tested) by Design and Characterization Data Parameter is typical value at TA e 25 C for information purposes only DC Electrical Characteristics TA e 25 C V a e B a e 15V Vb e Bb e b10V RSHUNT a e RSHUNTb e 6 5X no load Data E and OE from b1 6V to b 0 8V ISR e 800 mA VINH e 5V VINL e b 1 6V Parameter IS IS dis IVINH IVINL IDATA IOE IE VSR ISHUNT a ISHUNTb VSHUNT a VSHUNTb ISENSE VOS Sense Threshold at Shunts Sense Output Currents Output Offset Data High VINH e 0V VINL e b1 6V Data Low VINL e 0V VINH e 5V 160 1 b 50 b 100 Description (V a ) a (B a ) (Vb) a (Bb) Supply Currents (V a ) a (B a ) (Vb) a (Bb) Supply Currents Disabled Min Typ 52 17 Max 60 25 20 20 30 30 20 40 7 250 2 50 100 Test Level I I I I I I I I I I I I I Units mA mA mA mA mA mA mA mV mA mV mA mV mV TD is 2 7in b 20 b 20 b 30 b3 2 b 15 b 14 OE Input Current E Input Current Voltage at ISR Pin b 30 b 20 7 20 4 200 15 0 2 EL1056AC EL1056C Monolithic High-Speed Pin Driver DC Electrical Characteristics Contd TA e 25 C V a e B a e 15V Vb e Bb e b10V RSHUNT a e RSHUNTb e 6 5X no load Data E and OE from b1 6V to b 0 8V ISR e 800 mA VINH e 5V VINL e b 1 6V Parameter Eg NL PSRR Ro en Ro dis Io dis Io off Description Gain Error Data High VINH from 0V to 5V VINL e b1 6V No Load Data Low VINH e 5V VINL from b5V to 0V No Load Gain Nonlinearity Data High VINH from 0V to 10V VINL e b1 6V No Load Data Low VINH e 5V VINL from b10V to 0V No Load Power Supply Rejection Ratio of VOUT with Respect to B a Bb Shunt a or Shuntb Potential Output Resistance Enabled Il e g20 mA Output Resistance Output Disabled VO e b1 6V to b5V EL1056C EL1056AC Output Current Output Disabled VO e 0V Output Leakage E Low (Shut-Down) VO e 0V EL1056C EL1056AC 45 Min b1 5 b1 5 Typ b0 6 b0 6 Max 0 0 Test Units Level I I V V V % % % % mV V X X mA mA nA TD is 2 3in TD is 3 6in 0 04 0 06 22 6 75 I I 20K 100K 100K 200K b 20 b 20 b 150 5 20 20 150 I I I AC Electrical Characteristics TA e 25 C V a e B a e a 15V Vb e Bb e b10V RSHUNT a e RSHUNTb e 6 5X RL e 500X 50X a 22 pF snubber included at output Data E and OE from b1 6V to b0 8V ISR e 800 mA ECL swing is defined by VINH e b0 8V and VINL e b 1 6V CMOS swing defined by VINH e 5V and VINL e 0V Propagation delay is measured at 0 4V movement of output Parameter TPD Dis Description Propagation Delay CMOS Swing Propagation Delay Dispersion Due to Output Edge Direction From ECL to CMOS Swings Due to Repetition Rate Output Slew Rate CMOS Swing 20% - 80% Slew Rate Symmetry Output Rise Time ECL Swing 20% - 80% Output Overshoot CMOS Swing ECL Swing (ISR e 350 mA) Output Disable Delay Time Output Enable Delay Time Output Capacitance in Disable Power-Down Delay Time Power-On Delay Time Output Capacitance in Power-Down Comparator Delay Time Switching ON Switching Off 3 08 Min 10 Typ 30 250 250 80 1 3 22 190 65 47 60 3 05 90 50 15 04 500 65 85 Max 45 450 450 12 10 Test Level I I I V I I V I V I I V V V V V V Units ns ps ps ps V ns % ns mV mV ns ns pF ms ns pF ms ms SR SRsym TR OS Tdis Ten Co dis Toff Ton Co off Tsense EL1056AC EL1056C Monolithic High-Speed Pin Driver Block Diagram 1056 - 5 4 EL1056AC EL1056C Monolithic High-Speed Pin Driver Typical Performance Curves 10V CMOS TTL and ECL Outputs into 550X Load CMOS and ECL Outputs As Seen at the End of an Unterminated Cable Backmatched at Driver 1056 - 6 1056 - 7 CMOS Output at ISR e 100 mA 200 mA 400 mA and 1000 mA Output Slewrate vs ISR (Two Samples) 1056 - 8 1056 - 9 Propagation Delay vs ISR Output Slewrate vs Die Temperature 1056 - 10 1056 - 11 5 EL1056AC EL1056C Monolithic High-Speed Pin Driver Typical Performance Curves Propagation Delay Change with Die Temperature Contd Change in Propagation Delay with Power Supply Headroom 1056 - 12 Output Edge Dispersion vs Temperature 1056 - 13 Edge Dispersion vs ISR 1056 - 14 1056 - 15 Output Offset vs ISR Minimum Output Pulse Width 1056 - 16 1056 - 17 6 EL1056AC EL1056C Monolithic High-Speed Pin Driver Typical Performance Curves Tristate Turn-off Waveforms Contd Tristate Turn-on Waveforms 1056 - 18 1056 - 19 Power-Down Disable Waveforms Power-Down Enable Waveforms 1056 - 20 1056 - 21 Supply Current vs ISR Total Supply Current vs Supply Voltage 1056 - 22 1056 - 23 7 EL1056AC EL1056C Monolithic High-Speed Pin Driver Typical Performance Curves Mounted Thermal Resistance of Package vs Airflow Speed Contd Package Power Dissipation vs Ambient Temperature Sense Comparator Delay vs Overdrive 1056 - 24 1056 - 25 1056 - 26 EL1056 Used in CMOS and TTL Systems 1056 - 4 8 EL1056AC EL1056C Monolithic High-Speed Pin Driver Applications Information Functional Description The EL1056 is a fully integrated pin driver for automatic test systems Pin drivers are essentially pulse generators whose high and low levels can be externally programmed and accurately switched in time as well as incorporating an output switch to disconnect the driver from a measurement bus Additionally the EL1056 has programmable slewrate 1056 - 2 Control Voltage Inputs The analog level inputs are named VINH and VINL and the output replicates them as controlled by logic inputs The analog inputs are buffered and have bandwidths of 35 MHz and slewrates of 25V ms For full slewrate 4V of headroom should be given to the inputs that is VINH should be 4V less than V a or B a and VINL should be 4V more positive than V b or B b At lower slewrates (ISR e 500 mA or less) 3V of headroom will suffice Insufficient headroom causes distorted output waveforms or delay errors in output transitions VINH may be lower in voltage than VINL but the output will not follow the control logic correctly Furthermore VINH should be 200 mV more positive than VINL (the minimum output amplitude) for accurate switching 1056 - 3 Alternate Logic Interface Figure 1 Slewrate Control The slewrate is controlled by the ISR input This is a current input and scales the output slewrate by a nominal 1 25V ns mA The slewrate maintains calibration and symmetry to at least as slow as 0 2V ns The practical upper end of ISR is 1 mA and supply current increases with increasing ISR The ISR control can be used to adjust individual pin drivers to a system standard by adjusting the value of its series resistor Slewrate can also be slowed to reduce output ringing and crosstalk With ECL output swings there is not enough voltage excursion to incur slewrate delays to 50% logic threshold The risetime delays and dispersions do not degrade with reasonably reduced ISR and overshoot will reduce markedly An ISR of 350 mA produces a very good ECL output and driver dissipation is also reduced Logic Inputs The logic inputs are all differential types with both NPN and PNP transistors connected to each terminal They are optimized for differential ECL drive which optimizes a to b edge delay time matching Larger logic levels can introduce feedthrough glitches into the output waveform For CMOS input logic levels an ECL output waveform will show feedthrough when the input risetime is shorter than 8 ns differential or single-ended CMOS output swings show less aberration and the EL1056 can tolerate a 4 ns single-ended risetime or 2 ns risetime for differential inputs Attenuating CMOS or TTL inputs to 1 Vp-p will eliminate all logic feedthrough as shown in Figure 1 9 EL1056AC EL1056C Monolithic High-Speed Pin Driver Contd The ISR pin is connected to the emitter of a PNP transistor whose base is biased a diode below ground (see Figure 2) Thus the ISR input looks like a low impedance for positive input currents and is biased close to ground A protection diode absorbs negative currents and the input PNP will not conduct In power-down mode the PNP releases its current sink and the external circuit must not present more than 6V to the disabled ISR input or emitter-base damage to the NPN will occur within the driver A signal diode or zener can be used to clamp the ISR input for positive input voltages if the voltage on the ISR resistor is potentially greater than 6V when the driver is in power-down mode Applications Information a damaging potential Another benefit is that the capacitance seen at the output in tristate mode is reduced Because the tristate buffer's input is connected to the output terminal the output is quite ``alive'' during tristate For instance the input bias current of the buffer is seen as the tristate ``leakage'' and its variation with applied voltage becomes tristate input impedance The tristate input current is like a current source and it can drag an output to unpredictable voltages It is not a danger to connect a tristated output that has drifted to say b 6V to a logic pin of a device to be tested The tristate output current will simply comply with whatever voltage the connected part normally establishes The tristate input impedance is also quite active over frequency The output can oscillate when presented with resonant or inductive impedances To prevent this a snubber should be connected from output to ground consisting of a resistor in series with a small capacitor The snubber can also reduce the reflections of the coaxial line when driven from the far end since the line appears to have an open termination during tristate Typical values for the resistor are 50X to 75X and 12 pF to 22 pF for the series capacitor The effect of the snubber is to ``de-Q'' resonances at the output Output Stage-Tristate Mode In tristate mode (OE low) the output transistors have their emitter-base junctions reverse-biased by a diode voltage This turn-off voltage is in fact provided by an internal buffer whose input is connected to the output pin (see Figure 3) Transistors Q1 - Q4 form the output buffer in normal mode The tristate mode buffer Q5 - Q8 replicates externally impressed voltages from the output pin onto the internal schottky switch node They also turn off Q1 - Q4 by a reverse diode voltage between bases and emitters effectively bootstrapping the internal voltages so that no transistor's base-emitter junction is reverse-biased by 1056 - 27 Figure 2 ISR Pin Circuitry 10 EL1056AC EL1056C Monolithic High-Speed Pin Driver Applications Information Contd 1056 - 28 Figure 3 Output Stage Circuit in Tristate Mode Output Stage-Normal Mode Capacitive loads can cause the output stage to ring Little ringing occurs for loads less than 25 pF but substantial ringing for more than 40 pF Terminated transmission lines cause no ringing and actually suppress it as a snubber does A terminated line draws heavy DC current however and greatly raises dissipation Driving a back-terminated line also causes little ringing and does not cause DC dissipation The series matching resistor between the EL1056 output and a back-terminated line also serves to isolate the driver from capacitive loads and shortcircuits The slewrate of the driver slows by about 10% when driving a 50X back-matched 11 line as seen at the end of the line The snubber can be on either side of the back-match resistor When placed on the line side it creates a highfrequency termination for the line when the driver is tristated but it slows the output smallsignal risetime by about 10% (although not slewrate) When placed on the driver side of the backmatch resistor no speed reduction occurs in normal mode but the cable is more poorly terminated in tristate The transient currents that occur when driving capacitive or back-matched loads can be very high approaching 100 mA The driver is capable of outputting a peak of 140 mA but long-term EL1056AC EL1056C Monolithic High-Speed Pin Driver Applications Information Contd load currents must be limited to 60 mA Shortcircuits can rapidly destroy the EL1056 although the part will survive for 20 ms periods If there is the possibility of output load fault the overcurrent sense circuitry should be used to signal alarm to the controlling system which should ultimately activate the tristate mode to relieve the output stage Driving large static currents also raises internal dissipation and should be part of the thermal budget The collectors of the output transistors are connected to the Shunt terminals and the output stage drivers' collectors are connected to the B a and B b terminals (see Figure 4) The Shunt lines can have transient currents as high as 120 mA and are separated from the V a and V b terminals to keep switching noise out of the control and logic circuitry A bypass capacitor should be connected to the B a and B b terminals 1056 - 29 Figure 4 Output Stage in Normal Mode 12 EL1056AC EL1056C Monolithic High-Speed Pin Driver Applications Information Overcurrent Protection The sense comparators are available to alert the test system's controller that the driver is outputting excessive current Shunt resistors are connected from B a to Shunt a and B b to Shunt b When the internal comparators sense more than a nominal 200 mV drop on the shunts they cause a 1 5 mA current to be sunk from the Sense terminal The comparators are of ``slow attack fast decay'' design so that transient load currents will not trigger a sense output only a sustained overcurrent will The sense resistors must not be inductive and the skin resistance of long narrow connections between Shunt and B a or B b can cause transient voltages that produce output overshoot (but not ringing) The Sense output is simply a switched current source connected to V b It can be used to interface to CMOS TTL or ECL inputs For CMOS and TTL it can be connected to a pull-up resistor to a 5V of 10K value This establishes a logic high value and a clamp diode (internal to TTL) establishes a low level of b 0 6V For ECL a gate should be available to provide a static logic high level An 820X pull-up resistor is wired to that output The logic low will be more negative than is usual for ECL but this will cause no problem In all cases multiple Sense outputs may be connected together from many drivers to effect a wired-or function A further protection scheme is to provide a series resistor from B a to V a and B b to V b The resistor serves to limit the output fault current by allowing B a and B b voltages to sag under heavy load This also reduces the dissipation on the output transistors for valid loads Because Contd B a and B b are separately bypassed these voltages will sustain under transient loads and dynamics will not be affected Output Accuracy The accuracy of the output voltage depends on several factors The first is the gain error from VINH or VINL to the output unloaded The gain error is nominally b 0 6% and has a few tenths of a percent variation between parts The second is supply rejection If the B a B b Shunt a or Shunt b voltages are different from those used by Elantec to test the part there will be about 2 2 mV systematic shift in output offset per volt of supply variation The V a and V b supplies have much less influence on output error Finally there is a random VOS error as specified in the data table Of course the finite output impedance of the EL1056 will cause additional output error when the driver is loaded Power-Down The EL1056 incorporates a power-down feature that drastically reduces power consumption of an unused driver and also drops the output leakage current to nanoamperes (``A'' grade only) The output is not a low capacitance in this mode however and transients driven from the cable can momentarily turn on the output transistors Power-down is intended to allow the switching of accurate DC meters onto the bus without having to relay out the driver's leakage current It takes about 40 ms for the output leakage to sag to nanoamperes but this is still much faster than relays or voltmeters Power-down is controlled by the E and E differential inputs There is no problem with logic amplitude or slewrate and input resistor networks are not needed 13 EL1056AC EL1056C Monolithic High-Speed Pin Driver Power Down Contd Thermal Considerations The package of the EL1056 includes two fused leads on each side which are connected to the internal die mounting metal Heat generated in the die flows through the mounting pad to the fused leads and then to the circuit-board copper achieving a thermal resistance to air around 40 W Characterization curves show the thermal resistance versus airflow rate Consult the EL1056 Demonstration Board literature for a suggested board pattern Note that thicker layers of copper than we used improves the thermal resistance further to a limit of 22 C W for an ``infinite heatsink'' directly soldered to the fused leads As a practical limit the die temperature should be kept to 125 C rather than the allowable 150 C to retain optimum timing accuracies Supply and Input Bypassing The V a B a V b and B b leads should be bypassed very closely with 0 1 mF capacitors preferably chip type There should be a wide ground plane between bypasses and this can be the heatsink copper It is wise to also have a 4 7 mF tantalum bypass capacitor within a couple of inches to the driver The logic inputs are active device bases and can oscillate if presented with inductive lines A local resistor of 1000X or less to ground will suffice in de-Q'ing any resonance A 100 pF or larger capacitor can also serve as a bypass 14 BLANK 15 EL1056AC EL1056C EL1056AC EL1056C Monolithic High-Speed Pin Driver General Disclaimer Specifications contained in this data sheet are in effect as of the publication date shown Elantec Inc reserves the right to make changes in the circuitry or specifications contained herein at any time without notice Elantec Inc assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement WARNING Life Support Policy March 1993 Rev A Elantec Inc 1996 Tarob Court Milpitas CA 95035 Telephone (408) 945-1323 (800) 333-6314 Fax (408) 945-9305 European Office 44-71-482-4596 16 Elantec Inc products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec Inc Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death Users contemplating application of Elantec Inc products in Life Support Systems are requested to contact Elantec Inc factory headquarters to establish suitable terms conditions for these applications Elantec Inc 's warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages Printed in U S A |
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